The present invention relates to programmable logic devices ("PLDs"), and more particularly, to circuitry for interconnecting and driving signals onto various programmable logic device interconnects.
Programmable logic devices are well known as is shown, for example, by Pedersen et al. U.S. Pat. No. 5,260,610 and Cliff et al. U.S. Pat. No. 5,260,611.
There is continued interest in programmable logic devices with greater logic capacity. This calls for devices with larger numbers of regions of programmable logic. It also calls for logic devices with greater programmable interconnectivity for making needed connections between the increased numbers of logic regions. It is important, however, to organize interconnection resources judiciously so that those resources provide flexible interconnectivity, but do not begin to take up excessive amounts of space on the device, thereby unduly interfering with the amount of additional logic that can be included in the device. To accomplish this, it would be desirable to find ways to organize the interconnection resources on programmable logic devices so that the efficiency of utilization of the interconnection resources can be maximized. More interconnectivity could therefore be provided in the device to serve more logic in the device without simply adding more interconnection resources with the increased logic capability.
It is therefore an object of this invention to provide improved arrangements of interconnection resources for programmable logic devices.
It also an object of the invention to provide programmable logic device interconnection arrangements that can efficiently and flexibly interconnect larger numbers of programmable logic regions than previously possible.